vpi-sys cargo 0.7.0 clean Low-level FFI bindings to the Verilog and SystemVerilog VPI C API, generated with bindgen. This crate is not intended for direct use; use the safe `vpi` crate… 2.6K 14h ago vpi cargo 0.7.0 clean Safe and ergonomic Rust bindings to the Verilog and SystemVerilog VPI C API for writing VPI applications in Rust. 2.5K 14h ago vpi-shim cargo 0.7.0 clean Runtime symbol shim for VPI plugins on platforms that require explicit symbol resolution. 1.1K 14h ago sv-lang cargo 0.1.11+slang.12.0 clean Safe, ergonomic Rust bindings to slang, the fast SystemVerilog compiler frontend 205 1d ago sv-lang-sys cargo 0.1.6+slang.12.0 clean Raw FFI bindings to slang-c, the stable C API of the slang SystemVerilog compiler frontend 175 1d ago astli-text cargo 0.3.0 clean Files, spans, and macro-expansion provenance for SystemVerilog tooling 153 14h ago astli-syntax cargo 0.3.0 clean Lossless syntax tree, lexer, and preprocessor for SystemVerilog 146 14h ago sv-lang-kinds cargo 0.1.2+slang.12.0 clean Generated kind enums (syntax, token, trivia, diagnostic) for slang, the SystemVerilog compiler frontend 140 1d ago astli-preproc cargo 0.3.0 clean Directives, macro expansion, and `include resolution for SystemVerilog 137 14h ago astli-parse cargo 0.3.0 clean Event-based parser building a lossless SystemVerilog syntax tree 130 14h ago astli-fmt cargo 0.3.0 clean SystemVerilog formatter that leaves the preprocessed meaning unchanged 118 14h ago astli-diag cargo 0.3.0 clean Rendering a SystemVerilog diagnostic: snippets, and the chains that explain them 116 14h ago sv-lang-wasm cargo 0.1.6+slang.12.0 clean Run slang in a WebAssembly sandbox via wasmtime — parse SystemVerilog with no native slang, no C++ toolchain 81 1d ago astli cargo 0.3.0 clean SystemVerilog language tooling: a lossless syntax tree, a preprocessor, and a formatter 73 14h ago astli-cli cargo 0.3.0 clean The astli command: SystemVerilog formatting, and a dump of each stage of the pipeline 59 14h ago astli-index cargo 0.3.0 clean The top-level names SystemVerilog files declare and use, and the files a design needs 33 14h ago 