| sp1-core-executor cargo | 6.9.0 | none | none | RISC-V executor for SP1 | 2M | 4d ago |
| numkong cargo | 7.8.5 | none | none | Portable mixed-precision math, linear-algebra, & retrieval library with 2000+ SIMD kernels for x86, Arm, RISC-V, LoongArch, Power, & WebAssembly | 247K | 8d ago |
| asmkit-rs cargo | 0.7.5 | none | none | Portable assembler toolkit for encoding x86/x64, AArch64, and RISC-V | 7.3K | 4d ago |
| thru-base cargo | 0.4.2 | none | none | Core Rust primitives for the Thru blockchain: key and address types, transaction builders, state proof helpers, and RPC config. | 4.5K | 17h ago |
| synth-backend-riscv cargo | 0.85.0 | none | none | RISC-V encoder, ELF builder, PMP allocator, and bare-metal startup for synth | 3.2K | 17h ago |
| zisk-riscv cargo | | – 1.3.2-alpha did not build | – | RISC-V instruction structures and parser for the ZisK zkVM | 2.9K | 5d ago |
| zisk-transpiler-riscv cargo | | – 1.3.2-alpha did not build | – | Transpiler from RISC-V to the ZisK instruction set | 2.8K | 5d ago |
| ziskemu cargo | | – 1.3.2-alpha did not build | – | RISC-V emulator that executes ZisK program ROMs and generates execution traces | 2.8K | 5d ago |
| ch32rv-dmi cargo | 0.19.0 | none | none | RISC-V Debug Module Interface layer for the ch32rv tool suite, with WCH-specific quirks isolated behind the DtmAccess boundary | 808 | 5d ago |
| ch32rv-target cargo | 0.19.0 | none | none | Generated CH32 RISC-V device database (chip detection, flash geometry, option byte layouts) for the ch32rv tool suite | 701 | 5d ago |
| rsleigh-gen-riscv cargo | 0.6.1 | none | none | rsleigh generated decoder for RISC-V 64 (internal — use rsleigh-api) | 675 | 2d ago |
| rsleigh-api cargo | | – 0.6.1 did not build | – | High-level API for rsleigh — decode instructions and emit P-code for x86, x86-32, AArch64, ARM32, MIPS32, RISC-V 64 | 603 | 2d ago |
| rusty_rtos_port cargo | 0.3.2 | none | none | The FreeRTOS ports remade in Rust: the deterministic sim port (the oracle harness), the Posix host port, and the Cortex-M, RISC-V and Xtensa ports — the only… | 377 | 9d ago |
| zisk-build cargo | | – 1.3.2-alpha did not build | – | Build tooling for compiling guest programs to RISC-V ELF for the ZisK zkVM | 354 | 4d ago |
| rvsim-core cargo | 2.0.0 | none | none | A high-performance cycle-accurate RISC-V 64-bit system simulator. | 172 | 6d ago |
| wickra-zk-methods cargo | 0.2.0 | none | none | The compiled wickra-zk guest program: the RISC-V ELF the prover runs and the image id the verifier pins, committed alongside the source that produces them. | 170 | 8d ago |
| rusty_rtos_port-riscv cargo | 0.3.2 | none | none | The Kairos RISC-V port: critical sections, the yield, stack initialisation and the machine-software-interrupt context switch for RV32. One of the crates in the… | 98 | 9d ago |
| disc-v cargo | 0.1.3 | none | none | A RISC-V disassembler | 33 | 1d ago |
| esp-riscv-rt-p4-pre-v3 cargo | | – 0.14.0-p4v13.1 did not build | – | Minimal runtime / startup for RISC-V CPUs from Espressif | 16 | 9d ago |
