Search 1 packages
| Packages1–1 of 1 | Version | Findings | Description | Downloads | When |
|---|---|---|---|---|---|
| reticle cargo | 0.0.5 | clean | A from-scratch VHDL / Verilog compiler in pure Rust: frontends, a unified IR, simulation, synthesis and FPGA/ASIC backends, with first-class IP integration. | 209 | 10h ago |
