The FreeRTOS ports remade in Rust: the deterministic sim port (the oracle harness), the Posix host port, and the Cortex-M, RISC-V and Xtensa ports — the only…
GitHub, GitLab, Azure DevOps, Bitbucket, Linear, and Jira clients for forgetop. Internal crate: no API stability guarantees, use the `forgetop` binary instead.
A from-scratch VHDL / Verilog compiler in pure Rust: frontends, a unified IR, simulation, synthesis and FPGA/ASIC backends, with first-class IP integration.
Editor-core library for faceting cutting instructions: preform, tiers, undo/redo, and live solid validation. No UI, no database, no rendering -- see the…
Pure-Rust Aave V3 domain crate: the updater chunk-loop (transactional apply of decoded Aave events under one rusqlite Transaction) + the position-analysis math…
Temporary fork of the sspi crate (Devolutions' Rust SSPI implementation) carrying MIT Kerberos interoperability fixes, published for krabka; it will be…
The ExecutionAdapter seam (ADR-025) — a pyo3-free crate owning the user-owned execution layer: the ExecutionAdapter trait + its value types (solve-result view,…