A from-scratch VHDL / Verilog compiler in pure Rust: frontends, a unified IR, simulation, synthesis and FPGA/ASIC backends, with first-class IP integration.
Editor-core library for faceting cutting instructions: preform, tiers, undo/redo, and live solid validation. No UI, no database, no rendering -- see the…
The compiled wickra-zk guest program: the RISC-V ELF the prover runs and the image id the verifier pins, committed alongside the source that produces them.
Data-driven core of Wickra Strategy-CI: golden-pin a strategy's backtest report, assert tolerances and invariant properties, and fuzz-test against seeded data…
Deterministic core of wickra-benchmark: recompute a curated (strategy, dataset) case with the pinned wickra-backtest engine and confirm its report and hash…
Deterministic core of wickra-gym: precompute a candle dataset into a fixed feature tensor once, then step a Gymnasium-style RL environment in O(1) with…
Prover and verifier for wickra-zk: runs the deterministic wickra-backtest inside a risc0 zkVM guest and turns a receipt into a trustless, data-hiding proof of…
Data-driven core of the Wickra Copilot: a serde ContextSpec folded over microstructure feed snapshots into a deterministic MarketContext of hard facts (price…
