kvbm-physical cargo not built 1.5.1 did not build Dynamo Inference Framework 295 1d ago rs-rich-ext cargo 0.0.14 clean Extensions for the `rich` Rust port: diagnostics, structured data, clap and tracing integration, diffs, workflow renderables and a plugin registry 295 1d ago greentic-cap cargo 1.2.0-dev.37454230684 clean Greentic capability workspace scaffold. 294 2d ago fridica-core cargo 0.5.2 clean Fridica's domain: threads, parent decisions and delegation, workers, machines and placement, delivery outcomes and attention policy 292 2d ago eval-magic cargo 0.11.1 1 vulnerability 1 One-stop CLI for running skill evals — measure whether an agent skill actually shifts behavior. 286 1d ago wickra-screener-core cargo 0.3.0 clean Data-driven core of the Wickra screener: a serde ScanSpec condition tree folded over a symbol universe with 497 O(1) streaming indicators. 279 2d ago outram-foam-basic-lib cargo 0.1.4 clean OpenFOAM primitive functions translated to Rust -- an independent OUTRAM PARK fork, not the official OpenFOAM software 278 1d ago wsi-dicom cargo 0.8.0 1 vulnerability 1 Convert whole-slide imaging files to DICOM VL Whole Slide Microscopy 276 1d ago ntk-peerservices cargo 0.1.9 clean Generic distributed-service substrate (DHT-over-topology) that Coordinator and ANDNA register on. 274 2d ago cosmic-ext-nib-model cargo 1.2.1 clean The document model behind Nib: schema, positions, steps, transactions 273 1d ago execsurface-policy cargo 1.0.0 clean Deterministic policy and verdict engine for AETHER X ExecSurface 269 1h ago microclaw-core cargo 0.9.0 clean Stable provider-neutral contracts and safety primitives for MicroClaw 268 14h ago guicons-cli cargo 0.13.0 clean CLI for editing icons.gui.toml and populating the icon cache 267 2d ago kcode-k1-daemon-code-services cargo 0.1.11 clean Open the daemon's process-owned RustCode and WebCode services 258 2d ago greentic-dw-embedding-openai-compatible cargo 1.2.0-dev.37603443005 clean OpenAI-compatible embedding provider for Greentic DW (Ollama, vLLM, etc.). 246 1d ago pocket-ic-harness cargo 16.0.0 clean A test harness for Internet Computer canisters using PocketIC. 246 1d ago wickra-terminal-core cargo 0.2.0 clean Data-driven core of the Wickra trading terminal: sources, O(1) state and panels that emit view-models. 244 2d ago wickra-xray-core cargo 0.2.0 clean Data-driven core of the Wickra X-Ray: a serde XraySpec folded over a recorded dataset into XrayFrame render data-models (footprint, order-book heatmap,… 244 2d ago greentic-dw-llm-openai-compatible cargo 1.2.0-dev.37603443005 clean Generic OpenAI-compatible LLM provider for Greentic DW. 243 1d ago greentic-dw-knowledge cargo 1.2.0-dev.37603443005 clean Shared knowledge (document-RAG) contract for Greentic DW. 242 1d ago indicatrix-vault cargo 0.7.0 clean SQLite-backed storage, data models, and local import/export for gemstone faceting design libraries. 234 19h ago indicatrix-net cargo 0.7.0 clean Wire protocol for offloading indicatrix spectral ray samples to a remote render worker: scene-state and radiance-buffer codecs, message framing, a… 225 19h ago lingxia-device-io cargo 0.21.0 clean Sessionless desktop device I/O for LingXia tools and hosts 224 1d ago fiftyone-device-detection-cloud cargo 4.5.8-4 clean Cloud device-detection engine that maps the cloud JSON response to DeviceData. 217 2d ago gripsack-policy cargo 0.45.0 clean gripsack decision kernels — pure, contract-checked policy functions (plan/0046) 216 3h ago bindizr-service cargo 0.1.0-rc.2 clean Application services for bindizr: zones, records, tokens, TSIG keys, DNSSEC, notifications, RFC 2136 and ExternalDNS workflows 215 2d ago telegenic cargo 2.0.0 clean Pure-Rust GenICam camera library 214 2d ago rs-rich-cli cargo 0.0.15 2 vulnerabilities 2 The `rich` executable: a Rust port of Python `rich-cli` 1.8.1 213 2d ago tsr_diagnostics cargo not built 0.3.0 did not build Generated TypeScript diagnostic codes and messages for tsr 212 3d ago reticle cargo 0.0.5 clean A from-scratch VHDL / Verilog compiler in pure Rust: frontends, a unified IR, simulation, synthesis and FPGA/ASIC backends, with first-class IP integration. 209 17h ago 