cargo / rlx-fpga
FPGA backend for RLX — per-graph datapath synthesis. IR → Verilog → bitstream.
0.2.18 did not build; the badge stands for .
| Releases1 | Findings | Build time | Built | |
|---|---|---|---|---|
| 0.2.18 | not built | 1h ago |
Open-Source Registry
Open-Source Registry
cargo / rlx-fpga
FPGA backend for RLX — per-graph datapath synthesis. IR → Verilog → bitstream.
0.2.18 did not build; the badge stands for .
| Releases1 | Findings | Build time | Built | |
|---|---|---|---|---|
| 0.2.18 | not built | 1h ago |